The present invention relates generally to embedded systems. In particular, the present invention provides methods and apparatus for upgrading firmware in an embedded system, without impacting the system. More specifically, the present invention enables an embedded system to be upgraded without any system downtime, by providing two banks of memory (application areas) in non-volatile programmable read only memory. A processor can boot up and run from either application area. A fixed vector table is provided, which, in cooperation with a software vector table, enables the processor to maintain proper interrupt vector addresses while being able to run from either application area. Upgraded firmware can be loaded into one application area while the system is running from the other application area. Resetting the processor allows the system to run the upgraded version of firmware.
A conventional embedded system is made up of three parts. A processor to run the code, a non-volatile memory to store the code, and a volatile memory to store data and temporary information the code uses. In most systems the volatile memory is random access memory (RAM) and the non-volatile memory is programmable read only memory (PROM). Variations of the PROM are the erasable programmable read only memory (EPROM) and the electrically erasable programmable read only memory (EEPROM). The processor could be any one of the thousands of commercially available parts chosen to suit the needs of the designer.
A number of years ago a new EPROM variation was developed, called flash electrically erasable programmable read only memory, or FLASH. FLASH provided fast re-programmability. FLASH was embedded in many systems to enable a user to reload code and to change the system to make improvements or bug fixes.
In a prior art embedded system developed by General Instrument Corporation of Horsham, Pa., USA, the assignee of the present invention, FLASH memory was used to enable quicker system upgrades. In this prior art embedded system, the FLASH memory was partitioned into two parts. The first half of FLASH was loaded with the present version of firmware. If an upgrade was required, the second half of FLASH was erased and loaded with a new version of firmware. The unit could then be reset and the code now operated out of the second half of FLASH. If a newer version of firmware was required the process could be repeated over and over again, always reloading the second half of FLASH and keeping the first half of FLASH as a fail-safe backup copy of the firmware.
The above process was accomplished by having an additional RAM on the circuit board. When the unit is first started, the processor checks a non-volatile memory location to determine which half to load from. It then loads the RAM from the selected section of the FLASH. The processor from this point on uses the RAM for code storage and data storage. This enabled the FLASH to be reprogrammed while the system was running. However, to facilitate this copying and reprogramming, additional circuitry was required on the board to: 1) control the addressing of the FLASH and RAM; 2) control the addressing of external data ports; and 3) control the location of the interrupt vector table (vector table). As a result, the parts count and board space requirements of such a system were increased.
The vector table holds the addresses of all the interrupt service routines (ISR). These ISRs are critical to the functioning of a system. An example of an ISR would be a timer or a clock. At predefined intervals the clock or timer expires and a register that maintains the time must be updated. This must happen quickly. If a register is not updated quickly, the clock would be wrong or a predefined event would not occur, causing an error. The way a computer insures that these kinds of errors do not occur is by using interrupts. An interrupt is a signal that interrupts the normal flow of instructions. For example, when a timer expires, a hardware interrupt is generated. The computer then jumps to a predefined address and executes the code at that point. The code at that point is called an ISR. These routines are very concise. After the ISR is executed, the code then returns to the point it was at before the interrupt occurred. The predefined address that the hardware jumps to when an interrupt is generated is maintained in the vector table. Each interrupt must have an entry in the vector table. In some systems the vector table is fixed to a certain location in the memory map. In others, it can be relocated by software.
In systems where the vector table is a fixed vector table, problems arise when the processor is provided with the ability to load from two different banks of code which may be running two different versions of firmware. Because the ISR""s starting address could be different in each version of firmware, the entries in the vector table would be different.
It would be advantageous to be able to run firmware from either bank of memory while still maintaining the fixed vector table. It would also be advantageous to provide a fixed vector table that is adaptable to any future version of the firmware. It would be further advantageous to be able to upgrade the firmware in one bank of memory while the system is running, without impacting the system performance. It would be even further advantageous to provide the above advantages in a single chip, thereby saving board space, reducing parts count, and reducing costs.
The methods and apparatus of the present invention provide the aforesaid and other advantages.
The present invention provides methods and apparatus for upgrading firmware in an embedded system, without impacting the system. More specifically, the present invention enables an embedded system to be upgraded without any system downtime, by providing two application areas in non-volatile programmable read only memory. A processor can boot up and run from either application area. A fixed vector table is provided, which, in cooperation with a software vector table, enables the processor to maintain proper interrupt vector addresses while being able to run from either application area. Upgraded firmware can be loaded into one application area while the system is running from the other application area. Resetting the processor allows the system to run the upgraded version of firmware.
In an example embodiment of the invention, a processor may be provided for use in an embedded system. A non-volatile programmable read only memory device may be provided which has a fixed vector table, a boot area for storing boot code, a first application area for storing firmware, and a second application area for storing firmware. A random access memory device (RAM) may be provided having a software vector table and a RAM application area. The fixed vector table may be programmed with a reset vector address and interrupt vector addresses. The reset vector address may point to the boot code in the boot area and the interrupt vector addresses may point to corresponding interrupt vector addresses in the software vector table. An upgraded version of firmware may be loaded into one of the first application area or the second application area. After the updated version of firmware is loaded, the processor may be reset in order to run the upgraded version of firmware. The software vector table may be filled with proper corresponding interrupt vector addresses for the interrupt vectors contained in the fixed vector table, as determined by the upgraded version of firmware.
The non-volatile programmable read only memory device may comprise a flash electrically erasable programmable read only memory device (FLASH). Those skilled in the art will recognize that other suitable types of non-volatile programmable read only memory devices may be utilized to the same effect.
A prior version of firmware may be running from one application area while the upgraded version of firmware is being loaded into the other application area.
An erasable programmable memory device (EPROM) or similar device may be provided which is used to determine the application area to be accessed after the resetting step.
The RAM application area may be loaded with data from the application area having the upgraded version of firmware.
The first application area may contain a first version of firmware and the second application area may contain a second version of firmware. The updated version of firmware may be loaded into either application area. The application area that does not receive the updated version of firmware may be used to store a backup copy of firmware. For example, the old version of firmware may be left in this application area, or this application area can subsequently be updated to so that the firmware in both application areas is the same.
In a preferred embodiment of the invention, the processor, the non-volatile programmable read only memory device, and the RAM are all provided in the form of a single integrated circuit.